Increased miniaturization of components, greater packaging density of integrated circuits (“ICs”), higher performance, and lower cost are ongoing goals of the computer industry. Semiconductor package structures continue to advance toward miniaturization, to increase the density of the components that are packaged therein while decreasing the sizes of the products that are made therefrom. This is in response to continually increasing demands on information and communication products for ever-reduced sizes, thicknesses, and costs, along with ever-increasing performance.
These increasing requirements for miniaturization are particularly noteworthy, for example, in portable information and communication devices such as cellular phones, hands-free cellular phone headsets, personal data assistants (“PDA's”), camcorders, notebook computers, and so forth. All of these devices continue to be made smaller and thinner to improve their portability. Accordingly, IC packages that are incorporated into these devices are required to be made smaller and thinner. The package configurations that house and protect IC require them to be made smaller and thinner as well.
In response to the demands for improved packaging, many innovative package designs have been conceived and brought to market. The multi-chip module has achieved a prominent role in reducing the board space used by modern electronics. However, multi-chip modules, whether vertically or horizontally arranged, can also present problems because they usually must be assembled before the component chips and chip connections can be tested. That is, because the electrical bond pads on a die are so small, it is difficult to test die before being fully assembled. Thus, when die are mounted and connected individually, the die and connections can be tested individually, and only known-good-die (“KGD”) that is free of defects is then assembled into larger circuits. A fabrication process that uses KGD is therefore more reliable and less prone to assembly defects introduced due to bad die. With conventional multi-chip modules, however, the die cannot be individually identified as KGD before final assembly, leading to KGD inefficiencies and assembly process yield problems.
Numerous package approaches stack multiple integrated circuit dice or package in package (PIP) or a combination. Other approaches include package level stacking or package on package (POP). Both concepts include stacking of two or more packages. KGD and assembly process yields are not an issue since each package can be tested prior to assembly, allowing KGD to be used in assembling the stack. But stacking integrated devices, package-in-package, package-on-package, or combinations thereof have assembly process difficulties caused by leaded packages having limited input and output (I/O) which limits its role 3D packaging. Current leaded packages also do not provide the flexibility to support the various integration and stacking options described earlier with the higher I/O count support.
Thus, a need still remains for an integrated circuit packaging system providing low cost manufacturing, improved yields, reduction of integrated circuit package dimensions, and flexible stacking and integration configurations. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.